A 20-Gb/s half-rate 4:1 multiplexer with multiphase clock architecture in 40-nm CMOS technology

Abstract

This paper presents a 20-Gb/s half rate 4:1 multiplexer (MUX) with multiphase clock (MPC) architecture in 40-nm CMOS technology. The MPC architecture employs quarter-rate four-phase clock generated by true phase single clock divider, which omits the phase adjuster and delay-matching buffers and thus reduces power consumption. Meanwhile, The MUX is implemented by purely digital circuits contributing to saving more power. The MUX is designed in 40-nm CMOS process with 1.1-V supply voltage. The simulation result demonstrates that data jitter is 4.1 ps peak-to-peak and the power consumption is only 4.86 mW. We also propose a new multiphase clock generator that achieves high frequency and consumes low power.