A 208-GHz Injection Locking Doubler Chain With 3.2% PAE and 2.9-mW Output Power in CMOS Technology

Abstract

This letter presents an injection locking doubler chain centered at 208 GHz in 65-nm CMOS technology. The doubler chain consists of a doubler and two injection locking oscillators (ILOs). The doubler uses push–push topology to generate wideband second-harmonic output. Both ILOs are based on T-embedding network oscillator for high gain and high efficiency. The measured injection locking range is 188.4–225.6 GHz with the input injection power less than 0 dBm. The peak output power with the minimum injection input is 4.6 dBm (2.9 mW), and the 3-dB bandwidth is 200–220 GHz (9.5%). The power consumption is 83 mW under 1.2-V supply, and the peak power-added efficiency (PAE) reaches 3.2% at 211 GHz. Moreover, the total size of the chip excluding pads is 530 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}\,\,\times200\,\,\mu \text{m}$ </tex-math></inline-formula> . To the best of the author’s knowledge, this work demonstrates the highest PAE among CMOS doubler chains in similar frequency ranges reported by far.