A 2.03-mW CMOS Image Sensor With an Integrated Four-Stacked Charge-Recycling Driver for Image Signal Transmission

Abstract

We propose a CMOS image sensor with a dedicated low-power imaging mode and low-power integrated transmitter. The proposed CMOS image sensor selectively operates in dual mode: a high-quality mode with a 1.5 V supply voltage of readout circuits to achieve a high signal-to-noise ratio (SNR), and a low-power mode with a 0.9 V supply voltage to support always-on imaging. To further reduce the power consumption in the low-power mode, a single-slope analog to digital converter (ADC) embeds a power cutoff scheme in the comparator and a two-step conversion with dual reference voltages. To alleviate the SNR degradation in the low-power mode, which inherently occurs from voltage scaling, a correlated multiple sampling technique that consumes negligible power overhead is implemented using the proposed window-counting scheme. To reduce the significant power consumption that occurs during image signal transmission, an integrated transmitter with four-stacked charge-recycling drivers is used so that four symbols are simultaneously transmitted with a shared supply voltage. A prototype CMOS image sensor with 680 × 520 pixels is fabricated using 110-nm CMOS image sensor technology. The fabricated CMOS image sensor consumes only 301 μW (at 15 fps) in the sensor core and 2.03 mW including the transmitter and phase locked loop (PLL) while generating low temporal random noise under 0.27 LSB with correlated multiple sampling.