A 200 V silicon-on-sapphire LDMOS structure with a step oxide extended field plate

Abstract

Fabrication of power integrated circuits on silicon-on-sapphire (SOS) substrates has rarely been considered before. Hence, there is a lack of research in lateral power devices integrated on SOS. Self-heating effects in existing silicon-on-insulator (SOI) lateral power devices degrade the device performance and their reliability. Use of SOS substrates could alleviate these problems though they would require a different approach in lateral power device engineering. This paper purposes a new power SOS LDMOS structure with reduced transient self-heating effects and enhanced current capability compared to the conventional SOI counterpart. The proposed lateral power structure integrated on SOS substrates is analyzed by electro-thermal simulations. The field plate is enlarged (extended field plate (EFP)) along the drift region, reaching the drain region. The EFP includes an oxide step which improves the “on-state resistance–breakdown voltage” trade-off ( R ONxS– V br).