A 200 mA CMOS low-dropout regulator with double frequency compensation techniques for SoC applications

Abstract

This paper presents a 200 mA low-dropout (LDO) linear regulator using two modified techniques for frequency compensation. One technique is that the error amplifier uses a common source stage with variable load, which is controlled by the output current, is served as the second stage for a stable frequency response. The other technique is that the LDO uses a pole-zero tracking compensation technique at the error amplifier to achieve a good frequency response. The proposed circuit was fabricated and tested in HJTC 0.18 μm CMOS technology. The designed LDO linear regulator works under the input voltage of 2.8–5 V and provides up to 200 mA load current for an output voltage of 1.8 V. The total error of the output voltage due to line and load variation is less than 0.015%. The LDO die area is 630 × 550 μm2 and the quiescent current is 130 μA.