Abstract
The architecture and performance of a 20-bit arithmetic processor based on the logarithmic number system (LNS) is described. The processor performed LNS multiplication and division rapidly and with a low hardware complexity. Addition and subtraction in the LNS require the support of a table lookup unit. A scheme is proposed to minimize this complexity using a partitioned memory (ROM) and a PLA (programmable logic array). For performance evaluation, the target technology is integrated Schottky logic. The processor is shown to compare well with, if not to outperform, existing floating point (FLP) processors of equivalent range and precision. The speed-power-product ratio of an equivalent FLP processor, compared with that of the LNS processor, is reported to be 20 to 1 in the case of the square and square-root operation and 1 to 1 in the case of addition and subtraction. For multiplication and division, this ratio is about 5 to 1. >
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