A 2 mW, 50 dB DR, 10 MHz BW 5<formula formulatype="inline"> <tex Notation="TeX">$\times$</tex></formula> Interleaved Bandpass Delta-Sigma Modulator at 50 MHz IF

Abstract

A 2 mW 50 dB-DR 10 MHz-BW bandpass (BP) delta-sigma $(\Delta\Sigma)$ modulator for a digital-IF receiver is presented. It is based on a power-efficient time-interleaved (TI) architecture, which uses a recursive loop and a feed-forward topology. To further improve its power-efficiency, the ADC employs inverter-based OTAs with the help of auxiliary inverters for extra gain. A 0.55 ${\rm mm}^{2}$ chip is fabricated in a 0.18 $\mu{\rm m}$ CMOS process. Measurements show that the prototype five-path TI BP $\Delta\Sigma$ modulator achieves 50 dB DR and 46 dB SNDR with 10 MHz bandwidth at 50 MHz IF while dissipating only 2 mW.