Abstract

This paper proposes a scalable and efficient frequency multiplication technique that synthesizes a multi-phase clock with finely adjustable output taps. It uses a pulse injection locked rotary traveling-wave oscillator (RTWO) with switched capacitors and complementary varactor pairs to achieve a 1.7–2-GHz tuning range and to implement the fine phase adjustment. The worst case phase-tuning resolution is 0.36°. The design is implemented in IBM’s 130-nm CMOS technology, and consumes a total power of 28.4 mW. Locked to a clean 679-MHz reference, it has a phase-noise performance of $-{\text {132 dBc/Hz}}$ at 100-kHz offset from 2.039 GHz. It achieves 39-fs integrated root mean square (rms) jitter from 1 kHz to 40-MHz offset, for a ${\text {Jitter}}^{2} \ast {\text {Power Figure of Merit}}$ (FOM) of $-{\text {251 dB}}$ .

Full Text
Paper version not known

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call