Abstract
In this paper, an all-digital differentially encoded quaternary phase shift keying (DEQPSK) direct sequence spread-spectrum (DSSS) transceiver is proposed. The transceiver consists of two parts: a baseband/IF spread-spectrum transmitter and a coherent intermediate frequency (IF) receiver. The center frequency of this IF receiver is 11 MHz and the sampling rate is 44 Msamples/s. Modulation/demodulation, carrier recovery, PN acquisition, and differential coding are all provided within a single chip. Functional optimization and architecture design were performed before layout implementation. The 0.8-/spl mu/m N-well CMOS chip has a complexity of 56000 transistors with a core area of 3.5/spl times/3.5 mm/sup 2/. Power dissipation is 92 and 145 mW at 2.6 and 3.3 V, respectively.
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