Abstract
In this paper, the design of a reconfigurable low-power low-pass Switched Capacitor Delta-Sigma (SC ΔΣ) modulator for GSM/UMTS standards used in an optimum low-IF(LIF)/Zero-IF(ZIF) receiver architecture is described. A new approach for obtaining the optimum modulator coefficients is developed which results in relaxed specifications of the circuit components, aggressive noise transfer function (NTF) and a signal transfer function (STF) with the blocker-rejection property. The modulator employs a second/third-order single-stage dual-quantizer structure. It achieves 85.6dB/57dB SNDR and -0.2dBFS/-0.05dBFS overload factor at 0.2/2MHz bandwidth for GSM/UMTS standards and consumes only 2mW/5mW from a single 1.8V supply in a 0.18µm 1P6M CMOS process. The maximum spread of the modulator capacitors is 105.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
