A 2.4-$\hbox{V} _{\rm pp}$ 60-Gb/s CMOS Driver With Digitally Variable Amplitude and Pre-Emphasis Control at Multiple Peaking Frequencies

Abstract

The design of a 60-Gb/s CMOS driver with input signal retiming is analyzed theoretically and validated experimentally. The output stage employs a modified distributed amplifier (DA) architecture with summation of both low-pass and reactively coupled bandpass signal paths along a 50-Ω output transmission line. The DA features digital variable gain amplifier (DVGA) cells to achieve broadband waveshape control with adjustable pre-emphasis at three different peaking frequencies. Binary-weighted MOSFET gate-finger groupings are employed in a Gilbert-cell based DVGA topology to minimize bit-dependent output impedance and group delay variations. <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> -parameter measurements of the retimed driver show 54-dB gain, while the standalone DA exhibits approximately 10 dB of peaking control in each of the three frequency bands. Input and output return loss is better than -10 dB up to 60 GHz. The circuit operates from 1.2- and 2-V supplies and achieves a throughput efficiency of 12.2 mW/Gb/s. Equalization experiments at 40 Gb/s demonstrate compensation of various channel characteristics, including over 12 feet of cascaded coaxial cables with 21 dB loss at 20 GHz.