A 2.4-GHz 6.4-mW Fractional-N Inductorless RF Synthesizer

Abstract

A cascaded synthesizer architecture incorporates a digital delay-line-based filter and an analog noise trap to suppress the quantization noise of the $\Sigma \Delta $ modulator. Operating with a reference frequency of 22.6 MHz, the synthesizer achieves a bandwidth of 10 MHz in the first loop and 12 MHz in the second, heavily suppressing the phase noise of its constituent ring oscillators. Realized in 45-nm digital CMOS technology, the synthesizer exhibits an in-band phase noise of −109 dBc/Hz and an integrated jitter of 1.68 psrms.