A 2.24-pJ/bit 2.5-Gb/s UWB receiver in 28-nm FDSOI CMOS for low-energy chip-to-chip communications

Abstract

Chip-to-chip communications in high-performance applications such as server racks rely on wireline serial links. In this paper, we present a compact ultra-wideband receiver front-end in 28-nm FDSOI CMOS technology as a wireless interconnect alternative for low-energy and broadcast communications. It is based on binary pulse position modulation without guard interval using two periods of a 10-GHz carrier to reach 2.5-Gb/s datarate over distances >20 cm. The proposed receiver occupies 0.3 mm2 (including decoupling capacitors) and consumes only 5.6 mW which results in an energy of 2.24 pJ/bit.