A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability

Abstract

A general-purpose phase-locked loop (PLL) with programmable bit rates is presented demonstrating that large frequency tuning range, large power supply range, and low jitter can be achieved simultaneously. The clock recovery architecture uses phase selection for automatic initial frequency capture. The large period jitter of conventional phase selection is eliminated through feedback phase selection. Digital control sequencing of the feedback enables accurate phase interpolation without the traditional need of analog circuitry. Circuit techniques enabling low Vdd operation of a PLL with differential delay stages are presented. Measurements show a PLL frequency range of 1-200 MHz at Vdd=1.2 V linearly increasing to 2-1600 MHz at Vdd=2.5 V, achieved in a standard process technology without low threshold voltage devices. Correct operation has been verified down to Vdd=0.9 V, but the lower limit of differential operation with improved supply-noise rejection is estimated to be 1.1 V.