Abstract
A 10-bit successive approximation (SAR) analog-to-digital converter (ADC) in 90nm CMOS dedicated for sample rate limited applications is presented. The SAR ADC achieves an extra low energy by applying only one pre-opamp and without any low voltage techs in preserving the desired low power. HSPICE simulation results show that at a supply voltage of 1V and an output rate of 2.52kS/s, the SAR ADC performs a peak signal-to-noise-and-distortion ratio of 56.8dB. Our SAR ADC consumes 367nW in the simulation, corresponding to a figure of merits of 258.1fJ/conversion-step. And at lowest sample rate mode with an output rate of 126S/s, the ADC consumes only 21nW.
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