Abstract
The analog front-end in a wireless transceiver acts as the interface between the antenna and the digital signal processor. In the digital signal processor, low power is essential, making submicron CMOS technology the best implementation choice. The analog front-end and specifically the low noise amplifier (LNA) require a high speed technology, such as GaAs or silicon bipolar. However, the use of low-cost submicron CMOS or SOI CMOS technology in the analog front-end may lead to an optimum single chip implementation of both the analog and digital building blocks in wireless transceivers used in modern high capacity mobile communication systems. Such an implementation offers reduced cost and improved reliability. This paper describes a 1 V, 0.5 /spl mu/m SOI CMOS LNA optimized for CDMA applications and operating in the 1.93-1.99 GHz band. Compared to previously reported designs (Johnson et al., 1998; Komurasaki et al., 1998; Jin et al., 1999; Harada et al., 2000), this design offers lower noise, high gain, low intermodulation distortion and on-chip 50 /spl Omega/ input output impedance matching.
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