A 1K-gate GaAs gate array

Abstract

The successful design and fabrication of 1050-gate arrays are reported. Chip size is 3.75/spl times/3.75 mm. A basic cell can be programmed as an enhancement/depletion-type DCFL three-input NOR gate. The speed performance was measured at 0.2-mW/gate power dissipation. Unloaded (fanout=1) propagation delay time was 100 ps/gate. Load dependence of the delay time was 65 ps/1 mm interconnection line, 27 ps/fanout, and 3.33 ps/crossover load. This leads to 350 ps/gate delay under the assumed loading condition of interconnection line length=3 mm and three fanouts. The gate array was applied to 6/spl times/6 bit parallel multiplier circuit. The 10.6-ns multiplication time was measured at 380-mW power consumption. The operation speed of the personalized circuit can be well described by the basic performance provided by ring oscillator measurements.