A 1-GHz low-power transposition memory using new pulse-clocked D flip-flops

Abstract

This paper presents the design of a 1-GHz transposition memory (TRAM) that is designed in a 3.3-V 0.35-/spl mu/m CMOS technology. This high-speed TRAM is designed with the DFF-based architecture, and a new true-single-phase pulse-clocked D flip-flop (DFF) is developed to help achieve low power besides the high-speed performance. The new DFF is evolved from the true-single-phase-clocked (TSPC) split-output D latch, but the clock signal to the latch is locally processed to let the latch to behave as a DFF. The new DFF has a simpler circuit structure and less number of transistors triggered by the clock signal as compared to the previously reported high-speed semidynamic DFF (SD DFF). Therefore, when applying this new DFF to the TRAM, the power consumption of constituent DFFs and the clock driver in the TRAM can be reduced. The TRAM of this work has the same maximum operating frequency as the other TRAM designed with the SD DFFs, but 15% of the power is saved for the new design.