Abstract
This paper presents a fully integrated Peripheral Component Interconnect (PCI) Express (PCIe) Gen4 physical layer (PHY) transmitter. The prototype chip is fabricated in a 28 nm low-power CMOS process, and the active area of the proposed transmitter is 0.23 mm2. To enable voltage scaling across wide operating rates from 2.5 Gb/s to 16 Gb/s, two on-chip supply regulators are included in the transmitter. At the same time, the regulators maintain the output impedance of the transmitter to meet the return loss specification of the PCIe, by including replica segments of the output driver and reference resistance in the regulator loop. A three-tap finite-impulse-response (FIR) equalization is implemented and, therefore, the transmitter provides more than 9.5 dB equalization which is required in the PCIe specification. At 16 Gb/s, the prototype chip achieves energy efficiency of 1.93 pJ/bit including all the interface, bias, and built-in self-test circuits.
Highlights
Because Peripheral Component Interconnect Express (PCIe) is one of the most fastevolving high-speed interface standards, there are a lot of design challenges to meet PCIe Gen4 physical layer (PHY) transmitter specification
The energy efficiency is expected to be flat across the data rate [6], which is rarely achieved in conventional fixed-voltage designs
As a result, considering that a substantial portion of the power is dissipated by the dropout of regulators, we can conclude portion of the power is dissipated by the dropout of regulators, we can conclude that the proposed transmitter achieves the best efficiency among the supply-scalable transmitters
Summary
Because Peripheral Component Interconnect Express (PCIe) is one of the most fastevolving high-speed interface standards (for example the per-pin data rate is doubled every 4 years [1]), there are a lot of design challenges to meet PCIe Gen physical layer (PHY) transmitter specification. The overall energy efficiency is worse at a low signaling energy increases at a high data rate due to equalization p hand, the supply scaling allows improving the energy efficiency at shown, where a linear voltage–frequency scaling is assum contribution from the dynamic switching is significantly reduced at and the static current becomes less efficient because a fixed power is consumed regardless energy efficiency curve becomes flatter compared to Figure 1a, in of the data rate. The contribution from the dynamic switching is significantly reduced at a low data rate, rication results in a 28 nm CMOS, which offers the supply-voltage sc the energy efficiency curve becomes flatter compared to Figure 1a, in addition to the all the requirements.
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