Abstract
This paper describes a CMOS analog baseband circuits for direct-conversion receiver of5GHz IEEE 802.11a. The analog baseband consists of I/Q signal paths which have channel selection filter, programmable gain amplifier (PGA). An active-RC channel selection filter for WLAN is described whose cut-off frequency is tunable from 6MHz to 20MHz. This frequency tuning range is sufficient to cover IEEE802.11a (20MHz) including the effect of process, voltage, temperature variations. For wide tuning range, a differential R-2R ladder has been developed which gives widely variable resistance with minimum silicon area. Wide bandwidth operational amplifier (op-amp) is designed to dissipate small power by employing a current re-using feed forward frequency compensation scheme. For high linearity, the PGA is constructed with op-amp and resistor based inverting amplifiers. For minimum power consumption, the op-amps employ the current re-using feedforward frequency compensation. The input third-order intercept point (iIP3) is 20dBV at the highest gain mode. The input referred noise is 13 √ at the lowest gain mode. Implemented in a 0.18 m CMOS technology, the gain of the programmable gain amplifier (PGA) can be controlled from 2.5dB to 52.5dB with 0.5dB step.
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