A 1.8-V 67mW 10-bit 100MSPS pipelined ADC using time-shifted CDS technique

Abstract

A time-shifted correlated double sampling (CDS) technique is proposed in the design of a 10-bit 100 MSPS pipelined ADC. This technique significantly reduces the finite opamp gain error without compromising the conversion speed, allowing the active opamp block to be replaced by a simple cascoded CMOS inverter. Both high speed and low power operation is demonstrated without compromising the accuracy requirement. An efficient common-mode voltage control is used in the pseudo-differential architecture to further reduced power consumption. Fabricated in a 0.18 /spl mu/m CMOS process, the prototype 10-bit pipeline ADC achieves 65 dB SFDR and 54 dB SNDR at 100 MSPS. The total power consumption is 67 mW at 1.8-V supply.