Abstract
To meet high bandwidth, high resolution, and low power applications, such as LTE system, a fourth-order continuous-time sigma delta modulator with 20MHz bandwidth, implemented in 130nm CMOS is presented. The modulator comprises active-RC operational-amplifier based loop filter, 4bit internal quantizer and three current steering feedback DACs. A three-stage amplifier with low power is designed to satisfy the requirement of high dc gain and high gain-bandwidth product (GBW) of the loop filter. Non-return-to-zeros (NRZ) DAC pulse shaping is utilized to reduce clock jitter sensitivity. Special layout technique guarantees the main feedback to reach 12bit match accuracy, avoiding DEM algorithm to induce excess loop delay. The experimental results achieve 64.6-dB peak SNR, and 66-dB dynamic range over a 20-MHz signal bandwidth when clocked at 480-MHz with 18-mW power consumption from a 1.2 V supply.
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