Abstract
This paper describes the design and performance of a 16- kbit charge-coupled serial memory device. The memory is organized in four blocks of 4 kbits each with on-chip decoding and is mounted in a 16-pin ceramic dual-in-line hermetic package. Each 4-kbit block is organized as a serial-parallel-serial (SPS) array. Operated at a data rate of 1 MHz the mean access time is 2 ms and the on-chip power dissipation is calculated to be 1.5 µW/bit with another 0.5 µW/bit being required in off-chip clock drivers. The maximum designed output data rate is 10 MHz. Compared to the serpentine and loop organized memory charge-coupled device (CCD), the SPS organization has the advantages of lower power dissipation, greater tolerance to process parameter variations, and higher output data rate. All inputs and outputs are TTL compatible. Write/recirculate control is provided on the chip as well as two-dimensional decoding to permit memory matrix organization with X, Y chip select control. All the on-chip peripheral circuits use dynamic MOS circuitry to minimize power consumption. The charge sensing on the chip is achieved with balanced regenerative sense amplifiers. The memory array uses the three-phase three-level polysilicon electrode structure, and the chip is fabricated using an MOS n-channel polysilicon gate process with self-aligned source, drain, and channel stop.
Published Version
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