A 1.6-GHz CMOS PLL with on-chip loop filter

J.F Parker,D Ray

doi:10.1109/4.661199

A 1.6-GHz CMOS PLL with on-chip loop filter

J.F Parker, D Ray

https://doi.org/10.1109/4.661199

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Journal: IEEE Journal of Solid-state Circuits	Publication Date: Mar 1, 1998
Citations: 59

#Phase Locked Loop #CMOS Phase Locked Loop + Show 8 more

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Abstract

A 1.6-GHz phase locked loop (PLL) has been fabricated in a 0.6-/spl mu/m CMOS technology. The PLL consists of an LC-tank circuit, divider, phase detector with charge pump, and an on-chip passive loop filter. When the oscillator is open loop, it exhibits -115 dBc/Hz phase noise at a 600-kHz offset from the carrier. The PLL occupies an active area of 1.6 mm/sup 2/ and dissipates 90 mW from a single 3-V supply.

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