Abstract
In this project shared memory architecture is designed with 16-core processors, which are connected in star topology and share common memory for program and data. Processor is expected to run at 160 MHz, with effective instruction cycle speed at 1MHz (160 x 1). Shared memory is called 16-Core memory as the memory has hex ports. Any processor can write/read from the memory at the same time. If collisions occur, they are handled by priority method. The main aim of the project is to design “A 16-Core Processor with Shared-Memory and Message-Passing Communications”. The processor has 16 processor cores and 2 memory cores. Message-passing communications are supported by the 3x6 2D Mesh NOC, and shared-memory communications are supported by shared memory units in the memory cores.
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