Abstract
In this paper the design of a 3rd-order 16 bit 20 kHz-bandwidth discrete-time ΣΔ modulator with voltage-controlled oscillator (VCO)-based quantizer is presented. This design is motivated by the trends towards die size and power consumption reduction together with performance robustness. In this direction, the flash converter embedded in a multi-bit ΣΔM is here replaced by a VCO and digital counter, resulting in a compact fully-digital quantizer implementation. This solution would greatly exploit the technology scaling. Moreover in the proposed feed-forward architecture all feed-forward paths are summed within the last integrator of the ΣΔ loop filter, thereby eliminating the need for an analog summation amplifier at the quantizer input The presented 3rd-order ΣΔM features 110 dB-SNR, 104 dB-SNDR (i.e. 16 bit-ENOB).
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