A 16-Bit 1-MS/s Pseudo-Differential SAR ADC With Digital Calibration and DNL Enhancement Achieving 92 dB SNDR

Abstract

This paper presents a 16-bit 1 MS/s pseudo-differential Successive-Approximation-Register Analog-to-Digital Converter (SAR ADC) achieving an ENOB of 15-bit. To accommodate the pseudodifferential input, a differential DAC utilizing both monotonic and traditional switching is designed. For both dynamic and static performance improvement, three techniques are proposed. First, a foreground digital selfcalibration method is described to eliminate the capacitor mismatch errors. Some of the LSBs capacitors are utilized to measure and calculate the bit weights of other capacitors. Second, a DNL enhancement technique is presented. The fractional value capacitors are used to subtract an analog voltage from the DAC before the conversion is finished, which cancels out the consequent effect when the fractional part of the digital output is discarded before final output. Third, a low-offset low-noise comparator is designed. A reset timer with DAC settling replica is proposed to make the pre-amplifier in the comparator to start to amplify the DAC summing node voltage right after the DAC has fully settled. A prototype ADC is fabricated in a 0.18-μm 5-V CMOS process. It measures a 92.3-dB SNDR and a 107.9-dB SFDR. The DNL and INL are within ±0.3 LSB and ±0.72 LSB, respectively. The overall power consumption, drawn from the 5 V power supply, is 40 mW.