A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates

N Tamba,A Anzai,A Uchida,T Kokubu,K Yamaguchi,H Nambu,K Akimoto,T Fujiwara,T Muraya,M Ohayashi,S Tsuji,A Kishimoto,M Odaka,N Handa,Toshiro Hiramoto ,Kazuki Watanabe ,Minoru Yoshida ,Shinya Ohmori ,Takeshi Igarashi ,Hisashi Hayashi ,Takahide Ikeda

doi:10.1109/4.328635

A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates

N Tamba, A Anzai + Show 19 more

https://doi.org/10.1109/4.328635

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Journal: IEEE Journal of Solid-state Circuits	Publication Date: Jan 1, 1994
Citations: 5

Affiliation: Hitachi (Japan)

#Emitter-coupled Logic #CMOS Memory Cells + Show 8 more

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Abstract

A 1.5-ns address access time, 256-kb BiCMOS SRAM has been developed. To attain this ultra-high-speed access time, an emitter-coupled logic (ECL) word driver is used to access 6-T CMOS memory cells, eliminating the ECL-MOS level-shifter time delay. The RAM uses a low-power active pull down ECL decoder. The chip contains 11-K, 60-ps ECL circuit gates. It provides variable RAM configurations and general logic functions. RAM power consumption is 18 W; chip power consumption is 35 W. The chip is fabricated by using a 0.5-/spl mu/m BiCMOS process. The memory cell size is 58 /spl mu/m/sup 2/ and the chip size is 11/spl times/11 mm. >

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