Abstract
This brief describes the design and implementation of a broadband high efficiency power amplifier in 2-um InGaP/GaAs heterojunction bipolar transistor (HBT) process. For good linearity, an active adaptive bias circuit based on current mirror is employed. In particular, a Class-J PA core with high harmonic suppression is adopted to achieve wideband high-efficiency performance. The output matching network is designed off chip and realized by surface mounted devices (SMD) to save chip area. Covering an area of 0.9 × 0.9 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the proposed power amplifier is designed with the output power of more than 37 dBm at a 4.5-V supply voltage. At the frequency band from 1.5 to 2.1 GHz, the small signal gain is higher than 30 dB and the simulated peak power added efficiency (PAE) of over 60% is attained. Moreover, the power amplifier shows harmonic suppression level of higher than 65 dBc across the second to fifth harmonics at the output power 1-dB compression point (OP1dB), which is highly competitive in Radio Determination Satellite Service (RDSS).
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