Abstract
A new architecture for phase-locked-loop frequency synthesizers which employs a switchable-capacitor array to tune the output frequency is proposed. It provides many advantages, including simplified analog circuitry, low supply voltage, low power consumption, small chip area, fast frequency switching and high immunity of substrate noise. A prototype is designed for 1.5 V and consumes 30 mW. The total chip area is 0.9/spl times/1.1 mm/sup 2/. The settling time is less than 150 /spl mu/sec and the phase noise is -118 dBc/Hz at 600 KHz offset.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
