A 1.5 GHz third generation Itanium/spl reg/ processor

J Stinson,S Rusu

doi:10.1109/isscc.2003.1234289

A 1.5 GHz third generation Itanium/spl reg/ processor

J Stinson, S Rusu

https://doi.org/10.1109/isscc.2003.1234289

Copy DOI

Publication Date: Feb 9, 2003

Citations: 8

Affiliation: Intel (United States)

#Explicitly Parallel Instruction Computing #Set Associative Cache + Show 8 more

Abstract
Full-Text PDF
Similar Papers

Abstract

A third-generation 1.5 GHz Itanium/spl reg/ processor implements the Explicitly Parallel Instruction Computing (EPIC) architecture and features an on-die 6 MB, 24-way set associative L3 cache. The 374 mm/sup 2/ die contains 410M transistors and is implemented in a dual-V/sub T/ 0.13 /spl mu/m technology having 6-level Cu interconnects with FSG dielectric and dissipates 130 W.

Full Text