Abstract
A low power and energy efficient transceiver architecture is introduced. It is implemented on a single chip intended for use in short range radios based on WPAN (IEEE 802.15.4) at 2.4 GHz. The transmitter is based on a constant envelope modulator built around a dual loop frequency synthesizer coupled through an injection locking mechanism. The core of the dual conversion receiver is realized by reconfiguring the transmitter building blocks. Techniques are presented for tuning the center frequency and bandwidth of the RF filter, as well as generating the required local oscillator frequencies. The transceiver is fabricated in a 0.18-mum standard CMOS process. The receiver achieves -83-dBm sensitivity and -25 dBm 1-dB compression point. The transmitter outputs -7-dBm QPSK signal, while carrier phase noise is better than -108-dBc/Hz at 5-MHz offset. Active mode power consumption is 11-mW and 14-mW in receive and transmit modes, respectively, on a 1.6-V supply.
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