A 14b, Twofold Time-Interleaved Incremental ΔΣ ADC Using Hardware Sharing

Abstract

High-resolution, single-loop incremental Delta-Sigma (I- $\Delta \Sigma $ ) ADCs require large oversampling ratios to sufficiently suppress quantization noise. This limits the bandwidth of most designs to the low-kHz range. To overcome this problem, the presented proof-of-concept design makes use of time interleaving two third-order I- $\Delta \Sigma $ modulators with embedded hardware sharing that helps to enhance the efficiency of the presented modulator. The modulator is fully reconfigurable in a way that both channels can either be operated time interleaved or independent from each other. This is a means of enhancing the flexibility and efficiency of the modulator depending on the application scenario. The presented design was fabricated in a 180nm technology node.