A 140-mV Variation-Tolerant Deep Sub-Threshold SRAM in 65-nm CMOS

Abstract

This paper presents a sub-threshold SRAM, which eliminates bitline (BL) leakage-induced read failures. The proposed architecture clamps the current ratio between differential BLs to a fixed value, thus permitting reliable ultra-low-voltage read-out. A de-multiplexed wordline interleaving scheme is presented to compensate for bitcell area overhead. The interleaving technique achieves 9% reduction in decoder area and 50% reduction in clock load within the decoder. A sense amplifier circuit with reduced sensitivity to process variations is proposed to further enhance the reliability of the differential read-out. Measurement results from a 1-kb SRAM, fabricated in an industrial 65-nm low-power CMOS process, show 13.1-kHz operation at 140 mV, with active read and leakage power figures of 30.5 and 28.1 nW, respectively.