A 1.3mW 8-bit Two-step Time-to-Digital Converter

Abstract

A 1.3mW 8-bit Two-step Time-to-Digital Converter (TDC) with 3.8-ps resolution is proposed. It combines the advantages of the SAR and Vernier TDCs to improve the resolution and the dynamic range while holding the low power. The proposed Two-step TDC cancels the time amplifier to avoid its nonlinear problem. The whole architecture consists of coarse conversion and fine conversion. The coarse conversion uses the structure of successive approximation register, and the fine conversion uses the structure of Vernier. In order to compose these two TDCs well, a residual time generating circuit and an absolute value circuit are proposed and designed. The TDC circuit conversion rate is 60MS/s. The DNL and INL are 0.46(LSB) and 2.3(LSB), respectively. The occupied area of TDC is 0.036mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .