A 13.56 MHz Radio Frequency Identification Transponder Analog Front End Using a Dynamically Enabled Digital Phase Locked Loop

Abstract

Received October 5 2009, Revised December 28 2009, Accepted January 22 2010 The analog front end (AFE) of a radio frequency identification transponder using the ISO 14443 type A standard with a 100% amplitude shift keying (ASK) modulation is proposed in this paper and verified by circuit simulations and meas‐urements. This AFE circuit, using a 13.56 MHz carrier frequency, consists of a rectifier, a modulator, a demodulator, a regulator, a power on reset, and a dynamically enabled digital phase locked loop (DPLL). The DPLL, with a charge pump enable circuit, was used to recover the clock of a 100% modulated ASK signal during the period. A high voltage lateral double diffused metal‐oxide semiconductor transistor was used to protect the rectifier and the clock recovery circuit from high voltages. The proposed AFE was fabricated using the 0.18 µm standard CMOS process, with an AFE core size of 350 µm × 230 µm. The measurement results show that the DPLL, using a demodulator output sig‐nal, generates a constant 1.695 MHz clock during the period of the 100% ASK signal. Keywords: Radio frequency identification, Analog front end, Amplitude shift keying, Digital phase locked loop 1. INTRODUCTION Recently, radio frequency identification (RFID) technology has become a key component in manufacturing, distribution industries, and banking services [1]‐[3]. Mobile RFID is widely used at the high frequency of 13.56 MHz, and in the ultra‐high frequency band from 860 to 960 MHz. The mobile RFIDs that use the 13.56 MHz carrier frequency are limited to near field communication, however this limitation is very useful in the protection of privacy and in personal authentication proc‐esses. These mobile RFIDs, using the ISO 14443 type A stan‐dard, use 100% amplitude shift keying (ASK) modulation to create a pause period. A normal clock recovery circuit has a difficulty in recovering the clock during the period. It should be noted that the ISO 14443 type A and type B meth‐ods have different modulation index values, 100% and 10%, respectively [1]. We propose a new circuit structure for an RFID trans‐ponder analog front end (AFE) which easily recovers the clock of a 100% modulated ASK signal using the ISO 14443 type A standard. A digital phase locked loop (DPLL) incorpo‐rating a charge pump enable circuit is used to recover the clock of a 100% modulated ASK signal during the pe‐riod. We also used a high voltage lateral double diffused metal‐oxide semiconductor transistor (LDMOST) [4] for the rectifier and clock recovery circuit of the DPLL at the point where the high input signal is directly applied. The proposed RFID transponder AFE was verified by circuit simulations and the measurements of a fabricated chip manufactured using the 0.18 µm complementary MOS (CMOS) standard process.