Abstract
In order to achieve monotonicity and a high-speed performance, a current-cell matrix configuration and a parallel decoding circuit with one-stage latches have been used. A deglitching circuit has been introduced in the decoding stages to guarantee a low glitch energy. P-channel devices used as current sources ensure a low noise level and a ground-referenced voltage output in a doubly terminated 75- Omega transmission line. Experimental results have shown that the maximum conversion rate is 130 MHz and the integral and differential linearity errors are less than 0.5 LSB. The maximum glitch energy is 50 pS-V. The DAC has been developed in a 1- mu m digital/analog CMOS technology. The entire circuit dissipates 150 mW at a 130-MHz conversion rate while operating from a single 5-V power supply.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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