A 1.2-V 100KS/S energy efficient supply boosted SAR ADC

Abstract

This paper presents a new energy efficient supply boosted (SB) successive approximation register (SAR) type analog-to-digital converter (ADC) designed in a high-Vth CMOS process. Supply boosting technique (SBT) improves input common mode range and minimum operation voltage of mixed-signal circuits even when threshold voltages are in the order of the supply voltage. A 10-bit SB- SAR ADC was designed and fabricated in a standard 0.5 μm, 5V, 2P3M, CMOS process in which threshold voltages of NMOS and PMOS devices are +0.8V and -0.9V, respectively. Fabricated SB-SAR ADC achieves effective number of bits (ENOB) of 8.24, power consumption of 6μW from a 1.2Volt supply. Measured figure of merit (FoM) was 163fJ and 196fJ per conversion-step for sampling rates of 80KS/s and 100KS/s, respectively.