Abstract
A 6-bit current-steering DAC in 40nm CMOS is presented for wideband communication systems. Owing to the proposed true single phase clock (TSPC) dynamic pipelined decoding logic, the DAC achieves sampling rate beyond 10GS/s in an optimized 4–2 segmentation without time interleaving. The unit cell layout including switch transistors, cascode transistor and current source is compacted to reduce parasitic capacitance and maintain high output impedance for wideband linearity. The proposed one-dimension (1-D) current source array (CSA) together with trunk output distribution enhances output bandwidth further. The DAC obtains spurious free dynamic range (SFDR) > 30dB over the entire Nyquist range at 12GS/s sampling rate. The core occupies the area of 0.035mm2 and consumes 110mW of power from 1.1V supply voltage.
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