Abstract
A 12-bit 8-4 segmented current-steering digital to analog converter (DAC) is presented in this paper. The designed DAC consumes low power compared to similar designs. The number of control signals and chip area are also decreased considerably. High performance of the proposed DAC owes to appropriate segmentation of the digital input bits and employment of a new nested Binary to Thermometer (BT) decoder which uses domino logic gates. The proposed decoder is deployed in 3 similar stages with repetitive gates and pipelining scheme. Therefore, total power dissipation of the DAC in 0.18 μm CMOS technology at the sample rate of 1 GHz is approximately 62 mWatt. The digital supply voltage is 1.2 V while the analog supply voltage is 1.8 V. In addition, over the output bandwidth of 500 MHz at 1GS/s, the spurious-free dynamic range (SFDR) reaches 60.8 dB.
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