Abstract
This paper describes a low-power fully differential cyclic analog-to-digital converter (ADC) for CMOS image sensor readout circuits. The Cyclic ADC with redundant signed digital (RSD) algorithm has various obviously advantages, such as simpler circuit configuration and more tolerance to offset error of comparator. An operational amplifier with gain-boosting is used to increase the accuracy of the ADC. A prototype ADC is fabricated in 0.15um 1P6M CMOS technology. The results indicate that the ADC has a signal-to-noise and distortion ratio (SNDR) of 72.4dB and a spurious free dynamic range (SFDR) of 80.4dB. The power dissipation is 140uW with a 5V supply, and the chip size is 9um×570um.
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