A 128-Channel High Performance Time-to-Digital Converter Implemented in an UltraScale FPGA

Abstract

A 128-channel time-to-digital converter (TDC) with decimation TDC architecture was implemented in a Xilinx UltraScale field programmable gate array (FPGA) and the performance of 16 TDC channels was evaluated. The TDC RMS time precisions were measured in the range of 4.7 – 5.6 ps, and TDC measurement throughput reaches 350 M events/second. The test results show that the decimation method, which we proposed in our previous work, can balance well TDC time precision and FPGA resource consumption, so that integrating a very high channel count TDC system into an FPGA with high performance is very practicable. FPGA based TDC has bright future in applications of particle physics experiments and nuclear medicine imaging.