A 120GHz Frequency Tripler with Improved Output Power in 40nm CMOS

Han Cui,Leijun Xu

doi:10.1109/iccs51219.2020.9336593

A 120GHz Frequency Tripler with Improved Output Power in 40nm CMOS

Han Cui, Leijun Xu

https://doi.org/10.1109/iccs51219.2020.9336593

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Publication Date: Dec 10, 2020

Affiliation: Jiangsu University

#Improved Output Power #Total DC Power Consumption + Show 8 more

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Abstract

This paper introduces a frequency tripler with improved output power in 40nm CMOS process. Low insertion loss and high balanced Baluns are designed for the input and output impedance matching. Meanwhile, LC series resonance is used to suppress the fundamental wave and improve the power of third harmonic wave. When the input power is 10dBm, the peak output power is 3.7dBm, the frequency conversion loss is 6.3dBm and the fundamental suppression ratio is 41dBc. The total DC power consumption is 9.6mW. The 3-dB bandwidth is 12GHz (115.5GHz~127.5GHz).

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