Abstract
In this paper, a full-digital heartbeat (HB) detection system-on-chip (SoC) with low-noise analog front end (AFE) is presented. With the use of transconductance bootstrap and source degradation, the noise of AFE can be greatly reduced. The SoC is implemented in a <tex>$0.18\mu \mathrm{m}$</tex> CMOS process and consumes <tex>$1.2\mu \mathrm{W}$</tex> from a 1.2V supply, of which AFE and heart rate detector consume <tex>$0.8\ \mu \mathrm{W}$</tex> and <tex>$0.4\ \mu \mathrm{W}$</tex>, respectively. Besides, the noise from 1Hz to 1kHz is only <tex>$1.7\ \mu V_{rms}$</tex>. The gain of instrument amplifier (IA) is 33dB, and the cutoff frequency of high and low frequency are 0.4Hz and 40kHz respectively.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
