Abstract
A high-density monolithic analog-to-digital converter (ADC) has been designed and tested. The ADC features small silicon area and low power consumption for use in multichannel circuits for massively parallel particle physics detectors. The tested chip contains a linear ramp, precision high-speed comparators, a pipelined counter, and double buffering storage latches fabricated in a 2- mu m, two polysilicon CMOS technology. The prototype integrated circuit successfully combines digital frequencies in excess of 70 MHz with analog signals smaller than 1 mV. Test results show 1/4096 root-mean-square errors at conversion rates above 30 kHz, with less than 4 mW/channel power dissipation. >
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