A 12-bit 10 MS/s SAR ADC using the extended C–2C capacitor array

Abstract

This paper presents a 12-bit 10 MS/s successive approximation register analog-to-digital converter (SAR ADC) based on the extended C–2C capacitor array. Compared with traditional C–2C method, it provides a better tradeoff between the area and resolution of the capacitor array, facilitates the layout design, and reduces the mismatch of the capacitor array. The SAR ADC is realized in a 55 nm CMOS process. For Nyquist input, the simulation results show that SNR, SFDR and ENOB of the SAR ADC are 73.6 dB, 83.3 dB and 11.9 bit respectively. After extracting parasitic parameters, the post-simulation results show that SNR is 63.8 dB, SFDR is 73.3 dB, and ENOB is 10.32 bit, respectively.