Abstract

A new Error Correcting Code (ECC) solution aiming to improve the reliability of NAND flash memory (NAND) is proposed. Implemented in Solid-State Drive (SSD) controller IC (Fabricated in TSMC65LP), it is confirmed that more than 1/10000 lower error rate without increasing redundant bits (parity) of conventional BCH code, and 1.7x longer endurance of SSD can be achieved. This solution consists of two independent techniques: MP-ECC, a Message-Passing ECC architecture; and PAC, a Parity Area Combined ECC scheme.

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