Abstract
This paper presents a high-power single-pole double-throw (SPDT) switch with a novel design methodology to achieve>10 Watts 1-dB compression point (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> ) and low level of insertion loss for sub-6-GHz related applications. Implemented in a 0.13-μm silicon-on-insulator (SOI) CMOS process, the proposed switch adopts an all-positive alternative independent biasing technique to alleviate negative biasing voltage requirements in conventional high-power designs, avoiding that extra power consumption and noise introduced by the negative voltage generator while improved the power handling capability about 3 dB than conventional switches. The design has achieved 0.5~6 GHz operation band, 0.7~1 dB insertion loss, and 20~34 dB isolation. P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> is better than 42 dBm that covers majority of the high-power industrial scientific medical (ISM) and fifth-generation (5G) mobile applications. Stacked-FETs technique is co-designed to further enhance power handling capability. In post-layout simulation with passive components simulated with full-wave solver. The core area is as compact as 0.36×0.66 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .
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