A 10-Gb/s CMOS Serial-Link Receiver using Eye-Opening Monitoring for Adaptive Equalization and for Clock and Data Recovery

Abstract

A 10-Gb/s receiver for chip-to-chip communication is presented which employs an eye-opening monitor for both adaptive equalization as well as digital clock and data recovery (CDR). The prototype circuit fabricated in 0.13-μm CMOS technology consumes about 164 mW (adaptive equalizer and CDR, excluding output buffers) at 1.2 V supply voltage and occupies about 0.39 × 0.39 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The CDR fulfills the SONET/SDH jitter tolerance requirements at a 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> -1 PRBS and a BER of < 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> . Successful adaptive equalization of a 30 cm (12") and 76 cm (30") channel on standard FR4 substrate is also demonstrated.