A 10-Bit, Low Power, Successive Approximation, Digitally Auto-Zeroed CMOS ADC Core for the NASA TRIO Smart Sensor System on a Chip

Abstract

In spacecraft applications there is a great need for robust analogue to digital converters (ADC) that can withstand the harsh space environment. Commercially available ADCs cannot operate in the space environment due to radiation effects. In this paper we present an ADC that has been developed for the NASA TRIO smart sensor system on a chip (SoC), a versatile low power device specifically designed for spacecraft data acquisition and telemetry of several types of sensors such as temperature, voltage/current transducers, radFETs, etc. It is required for the ADC to operate in excess of 300 Krad total ionizing dose and to be robust to single event upsets. The successive approximation topology was chosen and it was enhanced with a special auto-zeroing technique to compensate for possible lifetime offset errors. Due to the comparator design, a rail-to-rail input capability is achieved, a feature very useful in some type of Vdd ratio metric sensors. It has 10-bit resolution for a reference in the range 0.1 to Vdd + 1 V, and for power supply in the range 2.5 to 5.5 V; the positive reference terminal Vref+ is settable up to Vdd + 0.5 V and the negative voltage terminal is settable down to GND-0.5 V. The power dissipation is less than 2 mW at 50 Ksamlles/sec. The TRIO chip is used in several NASA spacecraft including CONTOUR, STEREO, MESSENGER, EUROPA, PLUTO, etc.